Design and Fabrication Techniques for 3-D Integrated Circuits

DARPA

The 3-D integration of systems through monolithic wafer stacking is an emerging technology that can alleviate power, delay, and area problems for digital circuits and can enable a host of new applications in the System-on-Chip design space. Currently, CAD tools for 3-D integration are severely lacking stagnating potentially explosive growth of the technology. To this end, GoofyFoot Labs developed TESI-3D, a CAD verification and design exploration suite to accurately and efficiently simulate 3-D ICs for issues that are of chief concern to 3-D designers: thermal, signal integrity, and reliability. TESI-3D provides crucial, actionable feedback on performance and reliability induced by wafer stacking across all stages of the design cycle.

High Throughput, Low Latency and Low Power FPGA for Software Defined and Cognitive Radio

U.S. Army - CERDEC

FPGAs have become one of the most popular implementation media for digital circuits on account of their low NRE costs, field programmability, and time to market advantages over ASICs. However, FPGAs' greatest strength -- reconfigurability -- is also the source of their low performance and high power consumption. GoofyFoot Labs developed the AMP 3D-FPGA, which achieves ASIC-like performance with significantly lower power consumption than conventional FPGA architectures. The AMP 3D-FPGA achieves 1.7-GHz peak performance while simultaneously reducing standby power consumption by 70% and dynamic power consumption by nearly 50% over other 65-nm FPGAs making it suitable for high performance and mobile domains. Additionally, the AMP 3D-FPGA provides added benefit to DoD applications because its innovative architecture improves its anti-tamper properties by making it more resilient to side-channel and fault attacks.